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semiconductor group -1 ics for chip cards intelligent 256-byte eeprom sle 4432/sle 4442 data sheet 07.95
edition 07.95 this edition was realized using the software system framemaker ? . published by siemens ag, bereich halbleiter, marketing- kommunikation, balanstra?e 73, 81541 mnchen ? siemens ag 1995. all rights reserved. attention please! as far as patents or other rights of third par- ties are concerned, liability is only assumed for components, not for applications, pro- cesses and circuits implemented within com- ponents or assemblies. the information describes the type of compo- nent and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. for questions on technology, delivery and prices please contact the semiconductor group offices in germany or the siemens companies and representatives worldwide (see address list). due to technical requirements components may contain dangerous substances. for in- formation on the types in question please contact your nearest siemens office, semi- conductor group. siemens ag is an approved cecc manufac- turer. packing please use the recycling operators known to you. we can also help you C get in touch with your nearest sales office. by agreement we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us un- sorted or which we are not obliged to accept, we shall have to invoice you for any costs in- curred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the semiconductor group of siemens ag, may only be used in life-support devices or systems 2 with the ex- press written approval of the semiconductor group of siemens ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effec- tiveness of that device or system. 2 life support devices or systems are in- tended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. if they fail, it is rea- sonable to assume that the health of the user may be endangered.
ics for chip cards intelligent 256-byte eeprom sle 4432/sle 4442 data sheet 07.95
this edition was realized using the software system framemaker ? sle 4432/sle4442 revision history: original version 07.95 previous releases: 01.94 page subjects (changes since last revision) editorial changes important: for further information please contact: siemens semiconductor group in munich, germany, key account service chip card ics and identsystem ics, tel.: + 49 89 4144-4362, fax + 49 89 4144-2360 the supply of this component does not include a licence for its use in smart card applications. this licence is due to: innovatron patents 137 boulevard de sbastopol, 75002 paris, france, fax + 33 1 40 13 39 09
general information semiconductor group 3 contents page 1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 transmission protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2.1 reset and answer-to-reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.2 operational modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3.1 read main memory (sle 4432 and sle 4442) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.2 read protection memory (sle 4432 and sle 4442) . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.3 update main memory (sle 4432 and sle 4442) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.4 write protection memory (sle 4432 and sle 4442) . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.5 read security memory (sle 4442 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.6 update security memory (sle 4442 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.7 compare verification data (sle 4442 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.4 psc verification (sle 4442 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.5 reset modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.6 break . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.7 failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.8 coding of the chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3 operational information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.2.2 operation range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.2.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.2.4 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.3 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9 4 package and dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
semiconductor group 4 published by semiconductor group siemens aktiengesellschaft ordering no. b116-h6695-g1-x-7600 printed in germany da 07952.
type ordering code package sle 4432 m2.2 on request wire-bonded module m2.2 sle 4432 c on request chip sle 4442 m2.2 on request wire-bonded module m2.2 sle 4442 c on request chip 1) values are temperature dependent, for further information please refer to your siemens sales office. intelligent 256-byte eeprom with write protect function intelligent 256-byte eeprom with write protect function and p rogrammable s ecurity c ode (psc) sle 4432 m2.2 features l 256 8-bit eeprom organization l byte-wise addressing l irreversible byte-wise write protection of lowest 32 addresses (byte 0 ... 31) l 32 1-bit organization of protection memory l two-wire link protocol l end of processing indicated at data output l answer-to-reset acc. to iso standard 7816-3 l programming time 2.5 ms per byte for both erasing and writing l minimum of 10 4 write/erase cycles 1) l data retention for minimum of ten years 1) l contact configuration and serial interface in accordance with iso standard 7816 (synchronous transmission) additional feature of sle 4442 l data can only be changed after entry of the correct 3-byte programmable security code (security memory) sle 4442 semiconductor group 5 07.95
sle 4432 sle 4442 semiconductor group 6 1 pin configuration (top view) pin definitions and functions sle 4432/sle 4442 comes as a m2.2 wire-bonded module for embedding in plastic cards or as a die for customer packaging. card contact symbol function c1 vcc supply voltage c2 rst reset c3 clk clock input c4 n.c. not connected c5 gnd ground c6 n.c. not connected c7 i/o bidirectional data line (open drain) c8 n.c. not connected m2.2 (card contacts)
sle 4432 sle 4442 semiconductor group 7 2 functional description block diagram
sle 4432 sle 4442 semiconductor group 8 2.1 memory overview figure 1 memory overwiew sle 4432 the sle 4432 consists of 256 x 8 bit eeprom main memory and a 32-bit protection memory with prom functionality. the main memory is erased and written byte by byte. when erased, all 8 bits of a data byte are set to logical one. when written, the information in the individual eeprom cells is, according to the input data, altered bit by bit to logical zeros (logical and between the old and the new data in the eeprom). normally a data change consists of an erase and write procedure. it depends on the contents of the data byte in the main memory and the new data byte whether the eeprom is really erased and/or written. if none of the 8 bits in the addressed byte requires a zero- to-one transition the erase access will be suppressed. vice versa the write access will be suppressed if no one-to-zero transition is necessary. the write and the erase operation takes at least 2.5 ms each. each of the first 32 bytes can be irreversibly protected against data change by writing the corresponding bit in the protection memory. each data byte in this address range is assigned to one bit of the protection memory and has the same address as the data byte in the main memory which it is assigned to. once written the protection bit cannot be erased (prom).
sle 4432 sle 4442 semiconductor group 9 sle 4442 additionally to the above functions the sle 4442 provides a security code logic which controls the write/erase access to the memory. for this purpose the sle 4442 contains a 4-byte security memory with an e rror c ounter ec (bit 0 to bit 2) and 3 bytes reference data. these 3 bytes as a whole are called p rogrammable s ecurity c ode (psc). after power on the whole memory, except for the reference data, can only be read. only after a successful comparison of verification data with the internal reference data the memory has the identical access functionality of the sle 4432 until the power is switched off. after three successive unsuccessful comparisons the e rror c ounter blocks any subsequent attempt, and hence any possibility to write and erase. 2.2 transmission protocol the transmission protocol is a two wire link protocol between the interface device ifd and the integrated circuit ic. it is identical to the protocol type s = a. all data changes on i/o are initiated by the falling edge on clk. the transmission protocol consists of the 4 modes: note: the i/o pin is open drain and therefore requires an external pull up resistor to achieve a high level. C reset and answer-to-reset C command mode C outgoing data mode C processing mode operational modes
sle 4432 sle 4442 semiconductor group 10 2.2.1 reset and answer-to-reset answer-to-reset takes place according to iso standard 7816-3 (atr). the reset can be given at any time during operation. in the beginning, the address counter is set to zero together with a clock pulse and the first data bit (lsb) is output to i/o when rst is set from level h to level l. under a continuous input of additional 31 clock pulses the contents of the first 4 eeprom addresses is read out. the 33rd clock pulse switches i/o to high impedance z and finishes the atr procedure. figure 2 reset and answer-to-reset 2.2.2 operational modes command mode after the answer-to-reset the chip waits for a command. every command begins with a start condition, includes a 3 bytes long command entry followed by an additional clock pulse and ends with a stop condition. C start condition: falling edge on i/o during clk in level h C stop condition: rising edge on i/o during clk in level h after the reception of a command there are two possible modes: C outgoing data mode for reading C processing mode for writing and erasing answer-to-reset (hex) byte 1 byte 2 byte 3 byte 4 do 7 do 0 do 15 do 8 do 23 do 16 do 31 do 24
sle 4432 sle 4442 semiconductor group 11 outgoing data mode in this mode the ic sends data to the ifd. the first bit becomes valid on i/o after the first falling edge on clk. after the last data bit an additional clock pulse is necessary in order to set i/o to high impedance z and to prepare the ic for a new command entry. during this mode any start and stop condition is discarded. processing mode in this mode the ic processes internally. the ic has to be clocked continuously until i/o, which was switched to level l after the first falling edge of clk, is set to high impedance level z. any start and stop condition is discarded during this mode. note: the rst line is low during the modes mentioned above. if rst is set to high during the clk low level any operation is aborted and i/o is switched to high impedance z (break). figure 3 operational modes
sle 4432 sle 4442 semiconductor group 12 2.3 commands command format each command consists of three bytes: beginning with the control byte lsb is transmitted first. figure 4 command mode the sle 4432 provides 4 commands which are listed in table 1 . additionally to these commands the sle 4442 provides 3 commands which can be found in table 2 . msb control lsb msb address lsb msb data lsb & & & & & & & & % % % % % % % % ( ( ( ( ( ( ( (
sle 4432 sle 4442 semiconductor group 13 table 1 byte 1 control byte 2 address byte 3 data operation mode b7 b6 b5 b4 b3 b2 b1 b0 a7-a0 d7-d0 0 0 1 1 0 0 0 0 address no effect read main memory outgoing data 0 0 1 1 1 0 0 0 address input data update main memory processing 0 0 1 1 0 1 0 0 no effect no effect read protection memory outgoing data 0 0 1 1 1 1 0 0 address input data write protection memory processing table 2 sle 4442 only 0 0 1 1 0 0 0 1 no effect no effect read security memory outgoing data 0 0 1 1 1 0 0 1 address input data update security memory processing 0 0 1 1 0 0 1 1 address input data compare verification data processing
sle 4432 sle 4442 semiconductor group 14 2.3.1 read main memory (sle 4432 and sle 4442) the command reads out the contents of the main memory (with lsb first) starting at the given byte address (n = 0255) up to the end of the memory. after the command entry the ifd has to supply sufficient clock pulses. the number of clocks is m = (256 C n) 8 + 1. the read access to the main memory is always possible. figure 5 read main memory address (decimal) main memory protection memory security memory (only sle 4442) 255 data byte 255 (d7 d0) C C : :C C 32 data byte 32 (d7 d0) C C 31 data byte 31 (d7 d0) protection bit 31 (d31) C : :: C 3 data byte 3 (d7 d0) protection bit 3 (d3) reference data byte 3 (d7 d0) 2 data byte 2 (d7 d0) protection bit 2 (d2) reference data byte 2 (d7 d0) 1 data byte 1 (d7 d0) protection bit 1 (d1) reference data byte 1 (d7 d0) 0 data byte 0 (d7 d0) protection bit 0 (d0) error counter command: read main memory control address data b7 b6 b5 b4 b3 b2 b1 b0 a7a0 d7d0 binary 00110000addressno effect hexadecimal 30 h 00 h ff h no effect
sle 4432 sle 4442 semiconductor group 15 2.3.2 read protection memory (sle 4432 and sle 4442) the command transfers the protection bits under a continuous input of 32 clock pulses to the output. i/o is switched to high impedance z by an additional pulse. the protection memory can always be read, and indicates the data bytes of the main memory protected against changing. figure 6 read protection memory address (decimal) main memory protection memory security memory (only sle 4442) 255 data byte 255 (d7 d0) C C :: C C 32 data byte 32 (d7 d0) C C 31 data byte 31 (d7 d0) protection bit 31 (d31) C :: :C 3 data byte 3 (d7 d0) protection bit 3 (d3) reference data byte 3 (d7 d0) 2 data byte 2 (d7 d0) protection bit 2 (d2) reference data byte 2 (d7 d0) 1 data byte 1 (d7 d0) protection bit 1 (d1) reference data byte 1 (d7 d0) 0 data byte 0 (d7 d0) protection bit 0 (d0) error counter command: read protection memory control address data b7 b6 b5 b4 b3 b2 b1 b0 a7a0 d7d0 binary 00110100no effectno effect hexadecimal 34 h no effect no effect
sle 4432 sle 4442 semiconductor group 16 2.3.3 update main memory (sle 4432 and sle 4442) the command programs the addressed eeprom byte with the data byte transmitted. depending on the old and new data, one of the following sequences will take place during the processing mode: C erase and write (5 ms) corresponding to m = 255 clock pulses C write without erase (2.5 ms) corresponding to m = 124 clock pulses C erase without write (2.5 ms) corresponding to m = 124 clock pulses (all values at 50 khz clock rate.) address (decimal) main memory protection memory security memory (only sle 4442) 255 data byte 255 (d7 d0) C C : :CC 32 data byte 32 (d7 d0) C C 31 data byte 31 (d7 d0) protection bit 31 (d31) C : ::C 3 data byte 3 (d7 d0) protection bit 3 (d3) reference data byte 3 (d7 d0) 2 data byte 2 (d7 d0) protection bit 2 (d2) reference data byte 2 (d7 d0) 1 data byte 1 (d7 d0) protection bit 1 (d1) reference data byte 1 (d7 d0) 0 data byte 0 (d7 d0) protection bit 0 (d0) error counter command: update main memory control address data b7 b6 b5 b4 b3 b2 b1 b0 a7a0 d7d0 binary 00111000addressinput data hexadecimal 38 h 00 h ff h input data
sle 4432 sle 4442 semiconductor group 17 figure 7 erase and write main memory figure 8 erase or write main memory if the addressed byte is protected against changes (indicated by the associated written protection bit) the i/o is set to high impedance after the clock number 2 of the processing.
sle 4432 sle 4442 semiconductor group 18 2.3.4 write protection memory (sle 4432 and sle 4442) the execution of this command contains a comparison of the entered data byte with the assigned byte in the eeprom. in case of identity the protection bit is written thus making the data information unchangeable. if the data comparison results in data differences writing of the protection bit will be suppressed. execution times and required clock pulses see update main memory. address (decimal) main memory protection memory security memory (only sle 4442) 255 data byte 255 (d7 d0) C C :: C C 32 data byte 32 (d7 d0) C C 31 data byte 31 (d7 d0) protection bit 31 (d31) C : : :C 3 data byte 3 (d7 d0) protection bit 3 (d3) reference data byte 3 (d7 d0) 2 data byte 2 (d7 d0) protection bit 2 (d2) reference data byte 2 (d7 d0) 1 data byte 1 (d7 d0) protection bit 1 (d1) reference data byte 1 (d7 d0) 0 data byte 0 (d7 d0) protection bit 0 (d0) error counter command: write protection memory control address data b7 b6 b5 b4 b3 b2 b1 b0 a7a0 d7d0 binary 00111100addressinput data hexadecimal 3c h 00 h 1f h input data
sle 4432 sle 4442 semiconductor group 19 2.3.5 read security memory (sle 4442 only) similar to the read command for the protection memory this command reads out the 4 bytes of the security memory. the number of clock pulses during the outgoing data mode is 32. i/o is switched to high impedance z by an additional pulse. without a preceeding successful verification of the psc the output of the reference bytes is suppressed, that means i/o outputs state l for the reference data bytes. figure 9 read security memory address (decimal) main memory protection memory security memory (only sle 4442) 255 data byte 255 (d7 d0) C C :: C C 32 data byte 32 (d7 d0) C C 31 data byte 31 (d7 d0) protection bit 31 (d31) C :: : C 3 data byte 3 (d7 d0) protection bit 3 (d3) reference data byte 3(d7 d0) 2 data byte 2 (d7 d0) protection bit 2 (d2) reference data byte 2(d7 d0) 1 data byte 1 (d7 d0) protection bit 1 (d1) reference data byte 1(d7 d0) 0 data byte 0 (d7 d0) protection bit 0 (d0) error counter (0,0,0,0,0,d2,d1,d0) command: read security memory control address data b7 b6 b5 b4 b3 b2 b1 b0 a7a0 d7d0 binary 00110001no effectno effect hexadecimal 31 h no effect no effect
sle 4432 sle 4442 semiconductor group 20 2.3.6 update security memory (sle 4442 only) regarding the reference data bytes this command will only be executed if a psc has been successfully verified before. otherwise only each bit of the error counter (address 0) can be written from 1 to 0. the execution times and the required clock pulses are the same as described under update main memory. 2.3.7 compare verification data (sle 4442 only) this command can only be executed in combination with an update procedure of the error counter (see psc verification). the command compares one byte of the entered verification data byte with the corresponding reference data byte. for this procedure clock pulses are necessary during the processing mode. figure 10 compare verification data command: update security memory control address data b7 b6 b5 b4 b3 b2 b1 b0 a7a0 d7d0 binary 00111001addressinput data hexadecimal 39 h 00 h 03 h input data command: compare verification data control address data b7 b6 b5 b4 b3 b2 b1 b0 a7a0 d7d0 binary 00110011addressinput data hexadecimal 33 h 00 h 03 h input data
sle 4432 sle 4442 semiconductor group 21 2.4 psc verification (sle 4442 only) the sle 4442 requires a correct verification of the programmable security code psc stored in the security memory for altering data if desired. the following procedure has to be carried out exactly as described. any variation leads to a failure, so that a write/erase access will not be achieved. as long as the procedure has not been successfully concluded the error counter bits can only be changed from 1 to 0 but not erased. at first an error counter bit has to be written to 0 by an update command ( see figure 11 ) followed by three compare verification data commands beginning with byte 1 of the reference data. a successful conclusion of the whole procedure can be recognized by being able to erase the error counter which is not automatically erased. now write/erase access to all memory areas is possible as long as the operating voltage is applied. in case of error the whole procedure can be repeated as long as erased counter bits are available. having been enabled, the reference data are allowed to be altered like any other information in the eeprom. the following table gives an overview of the necessary commands for the psc verification. the sequence of the shaded commands is mandatory. as shipped, the psc is programmed with a code according to individual agreement with the customer. thus, knowledge of this code is indispensable to alter data. command control address data remark b7b0 a7a0 d7d0 read security memory 31 h no effect no effect check error counter update security memory 39 h 00 h input data write free bit in error counter input data: 0000 0ddd binary compare verification data 33 h 01 h input data reference data byte 1 compare verification data 33 h 02 h input data reference data byte 2 compare verification data 33 h 03 h input data reference data byte 3 update security memory 39 h 00 h ff h erase error counter read security memory 31 h no effect no effect check error counter
sle 4432 sle 4442 semiconductor group 22 figure 11 verification procedure
sle 4432 sle 4442 semiconductor group 23 2.5 reset modes reset and answer-to-reset (compare 2.2.1) power on reset after connecting the operating voltage to vcc, i/o is high impedance z. by all means, a read access to any address or an answer-to-reset must be carried out before data can be altered. 2.6 break if rst is set to high during clk in state l any operation is aborted and i/o is switched to high impedance z. minimum duration of t res =5 m s is necessary to trigger a defined valid reset. after break the chip is ready for further operations. 2.7 failures behavior in case of failures: in case of one of the following failures, the chip sets the i/o to high impedance z after 8 clock pulses at the latest. possible failures: C comparison unsuccessful C wrong command C wrong number of command clock pulses C write/erase access to already protected bytes C rewriting and erasing of a bit in the protection memory 2.8 coding of the chip due to security purposes every chip is irreversibly coded by a scheme. by this way fraud and misuse is excluded. the relevant data are programmed in the memory area from address 0 to 31. afterwards the associated protection bits are programmed. as an example, figures 12 and 13 show atr and directory data of structure 1. when delivered, atr header, icm and ict are programmed. siemens programs also the aid. the aid (application identifier) consists of 5 byte rid (registered application provider identifier) administered by a national registration authority and of up to 11 byte pix (proprietary application identifier extension). there are two possibilities: the customers aid or siemens aid (only for sample quantities). depending on the agreement between the customer and siemens iccf can be also programmed before delivery.
sle 4432 sle 4442 semiconductor group 24 figure 12 synchronous transmission atr and directory data of structure 1
sle 4432 sle 4442 semiconductor group 25 figure 13 answer-to-reset for synchronous transmission coding of structure 1
sle 4432 sle 4442 semiconductor group 26 3 operational information 3.1 memory map the data bytes 0 to 31 can be protected against further changes by programming the associated protection bit 0 to 31. the sle 4442 allows data changing only after correct verification of the reference data bytes. reading of the data bytes and of the associated protection bits is always possible. 3.2 electrical characteristics 3.2.1 absolute maximum ratings note: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability, including eeprom data retention and write/erase endurance. in the operating range the functions given in the circuit description are fulfilled. address (decimal) main memory protection memory security memory (only sle 4442) 255 data byte 255 (d7 d0) :: 32 data byte 32 (d7 d0) 31 data byte 31 (d7 d0) protection bit 31 (d31) :: : 3 data byte 3 (d7 d0) protection bit 3 (d3) reference data byte 3 (d7 d0) 2 data byte 2 (d7 d0) protection bit 2 (d2) reference data byte 2 (d7 d0) 1 data byte 1 (d7 d0) protection bit 1 (d1) reference data byte 1 (d7 d0) 0 data byte 0 (d7 d0) protection bit 0 (d0) error counter (0,0,0,0,0,d2,d1,d0) parameter symbol limit values unit min. max. supply voltage v cc C0.3 6.0 v input voltage (any pin) v i C0.3 6.0 v storage temperature t stg C40 125 c power dissipation p tot 70 mw
sle 4432 sle 4442 semiconductor group 27 3.2.2 operation range 3.2.3 dc characteristics parameter symbol limit values unit test condition min. typ. max. supply voltage v cc 4.75 5.0 5.25 v C supply current i cc 310ma v cc =5v ambient temperature t a 070 cC parameter symbol limit values unit test condition min. typ. max. high level input voltage (i/o, clk, rst) v ih 3.5 v cc vC low level input voltage (i/o, clk, rst) v il 00.8v C high level input current (i/o, clk, rst) i ih 50 m a v ih =5v low level output current (i/o) i ol 1ma v ol = 0.4 v, open drain high level output current (i/o) i oh 50 m a v oh = 5 v, open drain input capacitance c i 10 pf
sle 4432 sle 4442 semiconductor group 28 3.2.4 ac characteristics the ac characteristics refer to the timing diagrams in the following. v ihmin and v ilmax are reference levels for measuring timing of signals. note: the listed characteristics are ensured over the operating range of the integrated circuit. typical characteristics specify mean values expected over the production spread. if not otherwise specified, typical characteristics apply at t a = 25 c and the given supply voltage. parameter symbol limit values unit test condition min. typ. max. rst high to clk setup time t 10 4 m s clk low to rst hold time t 11 4 m s rst high time (address reset) t 12 20 50 m s rst low to i/o valid time t 13 2.5 m s rst low to clk setup time t 14 4 m s clk frequency f clk 750khz clk rise time t r 1 m s clk fall time t f 1 m s clk high time t 15 9 m s clk low time t 16 9 m s clk low to i/o valid time t 17 2.5 m s reset time for break t 18 5 m s rst high to i/o clear time (break) t 19 2.5 m s i/o high time (start condition) t 1 10 m s clk high to i/o hold time t 2 4 m s i/o low to clk hold time (start condition) t 3 4 m s i/o setup to clk high time t 4 1 m s clk low to i/o hold time t 5 1 m s clk high to i/o clear time (stop condition) t 6 4 m s clk low to i/o valid time t 7 2.5 m s clk low to i/o valid time t 8 2.5 m s clk low to i/o clear time t 9 2.5 m s erase time t er 2.5 ms f clk =50khz write time t wr 2.5 ms f clk =50khz power on reset time t por 100 m s
sle 4432 sle 4442 semiconductor group 29 3.3 timing diagrams figure 14 reset and answer-to-reset figure 15 command mode
sle 4432 sle 4442 semiconductor group 30 figure 16 outgoing data mode figure 17 processing mode
sle 4432 sle 4442 semiconductor group 31 figure 18 break
sle 4432 sle 4442 semiconductor group 32 4 package and dimensions chip and package outlines wire-bonded module m2.2
sle 4432 sle 4442 semiconductor group 33 chip dimensions wafer size: 5" stepping size: 1820 1850 m m 2 scribe line: 80 m m pad size: 110 110 m m 2

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